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rev. 4155b?aero?06/03 1 features functionally and pin compatible with the atmel commercial and military at40kel series ultra high performance ? system speeds 60 mhz ? array multipliers > 32 mhz ? 18 ns flexible sram ? internal tri-state capability in each cell freeram ? ? flexible, single/dual port, sync/async 18 ns sram ? 18432 bits of distributed sram independent of logic cells for at40kel 384 pci compliant i/os ? programmable output drive ? fast, flexible array access facilitates pin locking 8 global clocks ? fast, low skew clock distribution ? programmable rising/falling edge transitions ? distributed clock shutdown capability for low power management ? global reset/asynchronous reset options ? 4 additional dedicated pci clocks cache logic ? dynamic full/partial reconfigurability in-system ? unlimited reprogrammability via serial or parallel modes ? enables adaptive designs ? enables fast vector multiplier updates ? quick-change ? tools for fast, easy design changes package options ? mqfpf160 industry-standard design tools ? seamless integration (libraries, interface, full back-annotation) with exemplar ? , mentor ? , synplicity ? ? timing driven placement & routing ? automatic/interactive multi-chip partitioning ? fast, efficient synthesis ? over 75 automatic component generators create 1000s of reusable, fully deterministic logic and ram functions intellectual property cores ? fir filters, uarts, pci, fft and other system level functions easy migration to atmel gate arrays for high volume production supply voltage 3.3v 100 krads (tm 1019.5) latch-up immune built-in seu hardening design tools ? atdh40m: mother board ? atdh40d160m: daughter board for mqfpf160 ? atds2100pc: ids software design kit ? atdh 2225: at17 series configuration memory isp download cable qml and scc quality grades rad hard reprogrammable fpgas with freeram ? at40kel preliminary
2 at40kel 4155b ? aero ? 06/03 *** note: 1. packages with fck will have 8 less clocks. description the at40kel is a fully pci-compliant, sram-based fpga with distributed 18 ns pro- grammable synchronous/asynchronous, dual port/single port sram, 8 global clocks, cache logic ability (partially or fully reconfigurable without loss of data), automatic com- ponent generators, and 50,000 usable gates. i/o counts range from 128 to 384 in aero- space standard packages and support 3.3v. the at40kel is designed to quickly implement high performance, large gate count designs through the use of synthesis and schematic-based tools used on a pc and sun ? platform. atmel ? s design tools provide seamless integration with industry standard tools such as synplicity, modelsim, exemplar and viewlogic. see the ids datasheet for other supported tools. the at40kel can be used as a co-processor for high-speed (dsp/processor-based) designs by implementing a variety of compute-intensive, arithmetic functions. these include adaptive finite impulse response (fir) filters, fast fourier transforms (fft), convolvers, interpolators and discrete-cosine transforms (dct) that are required for video compression and decompression, encryption, convolution and other multimedia applications. fast, flexible and efficient sram the at40kel fpga offers a patented distributed 11 - 13 ns sram capability where the ram can be used without losing logic resources. multiple independent, synchronous or asynchronous, dual port or single port ram functions (fifo, scratch pad, etc.) can be created using atmel ? s macro generator tool. fast, efficient array and vector multipliers the at40kel ? s patented 8-sided core cell with direct horizontal, vertical and diagonal cell-to-cell connections implements ultra fast array multipliers without using any busing resources. the at40kel ? s cache logic capability enables a large number of design coefficients and variables to be implemented in a very small amount of silicon, enabling vast improvement in system speed at much lower cost than conventional fpgas. cache logic design the at40kel is capable of implementing cache logic (dynamic full/partial logic recon- figuration, without loss of data, on-the-fly) for building adaptive logic and systems. as new logic functions are required, they can be loaded into the logic cache without losing the data already there or disrupting the operation of the rest of the chip; replacing or complementing the active logic. the at40kel can act as a reconfigurable co-proces- sor. automatic component generators the at40kel fpga family is capable of implementing user-defined, automatically gen- erated, macros in multiple designs; speed and functionality are unaffected by the macro orientation or density of the target device. this enables the fastest, most predictable and efficient fpga design approach and minimizes design risk by reusing already proven functions. the automatic component generators work seamlessly with industry-stan- table 1. at40kel device at40kel040 usable gates 40k - 50k rows x columns 48 x 48 cells 2,304 registers 3,048 (1) ram bits 2304 i/o (max) 384
3 at40kel 4155b ? aero ? 06/03 dard schematic and synthesis tools to create the fastest, most efficient designs avail- able. the patented at40kel series architecture employs a symmetrical grid of small yet powerful cells connected to a flexible busing network. independently controlled clocks and resets govern every column of cells. the array is surrounded by programmable i/o. devices offer 50,000 usable gates, and have 3,056 registers. at40k series fpgas uti- lize a reliable 0.35 single-poly, 4-metal cmos process and are 100% factory-tested. atmel ? s pc- and workstation-based integrated development system (ids) is used to cre- ate at40kel series designs. multiple design entry methods are supported. the atmel architecture was developed to provide the highest levels of performance, functional density and design flexibility in an fpga. the cells in the atmel array are small, efficient and can implement any pair of boolean functions of (the same) three inputs or any single boolean function of four inputs. the cell ? s small size leads to arrays with large numbers of cells, greatly multiplying the functionality in each cell. a simple, high-speed busing network provides fast, efficient communication over medium and long distances.
4 at40kel 4155b ? aero ? 06/03 the symmetrical array at the heart of the atmel architecture is a symmetrical array of identical cells (figure 1). the array is continuous from one edge to the other, except for bus repeaters spaced every four cells (figure 2 on page 5). at the intersection of each repeater row and col- umn is a 32 x 4 ram block accessible by adjacent buses. the ram can be configured as either a single-ported or dual-ported ram (1) , with either synchronous or asynchro- nous operation. note: 1. the right-most column can only be used as single-port ram. figure 1. symmetrical array surrounded by i/o (at40k20) note: at40kal has registered i/os. group enable every sector for tri-states on obuf ? s. = i/o pad = at40k cell = repeater row = repeater column = freeram
5 at40kel 4155b ? aero ? 06/03 figure 2. floorplan (representative portion) (1) note: 1. repeaters regenerate signals and can connect any bus to any other bus (all path- ways are legal) on the same plane. each repeater has connections to two adjacent local-bus segments and two express-bus segments. this is done automatically using the integrated development system (ids) tool. rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rh = vertical repeater = horizontal repeater = core cell ram ram ram ram ram ram ram ram ram ram ram ram ram ram ram ram
6 at40kel 4155b ? aero ? 06/03 the busing network figure 3 on page 7 depicts one of five identical busing planes. each plane has three bus resources: a local-bus resource (the middle bus) and two express-bus (both sides) resources. bus resources are connected via repeaters. each repeater has connections to two adjacent local-bus segments and two express-bus segments. each local-bus segment spans four cells and connects to consecutive repeaters. each express-bus segment spans eight cells and ? leapfrogs ? or bypasses a repeater. repeaters regener- ate signals and can connect any bus to any other bus (all pathways are legal) on the same plane. although not shown, a local bus can bypass a repeater via a programma- ble pass gate allowing long on-chip tri-state buses to be created. local/local turns are implemented through pass gates in the cell-bus interface (see following page). express/express turns are implemented through separate pass gates distributed throughout the array. some of the bus resource on the at40kel is used as a dual-function resource. table 2 shows which buses are used in a dual-function mode and which bus plane is used. the at40kel software tools are designed to accommodate dual-function buses in an effi- cient manner. table 2. dual-function buses function type plane(s) direction comments cell output enable local 5 horizontal and vertical ram output enable express 2 vertical bus full length at array edge bus in first column to left of ram block ram write enable express 1 vertical bus full length at array edge bus in first column to left of ram block ram address express 1 - 5 vertical buses full length at array edge buses in second column to left of ram block ram data in local 1 horizontal ram data out local 2 horizontal clocking express 4 vertical bus half length at array edge set/reset express 5 vertical bus half length at array edge
7 at40kel 4155b ? aero ? 06/03 figure 3. busing plane (one of five) = local/local or express/express turn point = at40k/40kal = row repeater = column express bus local bus express bus at40kel
8 at40kel 4155b ? aero ? 06/03 cell connections figure 4(a) depicts direct connections between a cell and its eight nearest neighbors. figure 4(b) shows the connections between a cell and five horizontal local buses (1 per busing plane) and five vertical local buses (1 per busing plane). figure 4. cell connections cel cel cel cel cel cel cel cel cel cel (a) cell-to-cell connections (b) cell-to-bus connections w x y z l wxyzl orthogonal direct connect diagonal direct connect ? ? ? ? ? ? ? ? ? ? horizontal busing plane vertical busing plane ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? plane 5 plane 4 plane 3 plane 2 plane 1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? plane 5 plane 4 plane 3 plane 2 plane 1
9 at40kel 4155b ? aero ? 06/03 the cell figure 5 depicts the at40kel cell. configuration bits for separate muxes and pass gates are independent. all permutations of programmable muxes and pass gates are legal. v n (v 1 -v 5 ) is connected to the vertical local bus in plane n. h n (h 1 -h 5 ) is con- nected to the horizontal local bus in plane n. a local/local turn in plane n is achieved by turning on the two pass gates connected to v n and h n . pass gates are opened to let sig- nals into the cell from a local bus or to drive a signal out onto a local bus. signals coming into the logic cell on one local bus plane can be switched onto another plane by opening two of the pass gates. this allows bus signals to switch planes to achieve greater routability. up to five simultaneous local/local turns are possible. the at40kel fpga core cell is a highly configurable logic block based around two 3- input luts (8 x 1 rom), which can be combined to produce one 4-input lut. this means that any core cell can implement two functions of 3 inputs or one function of 4 inputs. there is a set/reset d flip-flop in every cell, the output of which may be tri-stated and fed back internally within the core cell. there is also a 2-to-1 multiplexer in every cell, and an upstream and gate in the ? front end ? of the cell. this and gate is an impor- tant feature in the implementation of efficient array multipliers. figure 5. the cell with this functionality in each core cell, the core cell can be configured in several ? modes ? . the core cell flexibility makes the at40kel architecture well suited to most digital design application areas (see figure 6). out out reset/set clock fb 10 z d q "1" nw ne se sw "1" "1" "1" "0" xwy x zwy "1" n e s w 8x1 lut 8x1 lut x y nw ne se sw n e s w v1 h1 v2 h2 v3 h3 v4 h4 v5 h5 "1" oe h oe v l pass gates x = diagonal direct connect or bus y = orthogonal direct connector bus w = bus connection z = bus connection fb = internal feed back
10 at40kel 4155b ? aero ? 06/03 figure 6. some single cell modes lut lut lut lut lut 2:1 mux lut lut dq dq q q (registered) dq dq synthesis mode. this mode is particularly important for the use of vhdl design. vhdl synthesis tools generally will produce as their output large amounts of random logic functions. having a 4-input lut structure gives efficient random logic optimization without the delays associated with larger lut structures. the output of any cell may be registered, tri-stated and/or fed back into a core cell. arithmetic mode is frequently used in many designs. as can be seen in the figure, the at40k core cell can implement a 1-bit full adder (2-input adder with both carry in and carry out) in one core cell. note that the sum output in this diagram is registered. this output could then be tri-stated and/or fed back into the cell. dsp/multiplier mode. this mode is used to efficiently implement array multipliers. an array multiplier is an array of bitwise multipliers, each implemented as a full adder with an upstream and gate. using this and gate and the diagonal interconnects between cells, the array multiplier structure fits very well into the at40k architecture. counter mode. counters are fundamental to almost all digital designs. they are the basis of state machines, timing chains and clock dividers. a counter is essentially an increment by one function (i.e., an adder), with the input being an output (or a decode of an output) from the previous stage. a 1-bit counter can be implemented in one core cell. again, the output can be registered, tri-stated and/or fed back. tri-state/mux mode. this mode is used in many telecommunications applications, where data needs to be routed through more than one possible path. the output of the core cell is very often tri-statable for many inputs to many outputs data switching. a b c d a b c a b c d a b c en q q sum (registered) sum and/or product or carry product (registered) carry carry carry in and/or or and/or and/or
11 at40kel 4155b ? aero ? 06/03 ram 32 x 4 dual-ported ram blocks are dispersed throughout the array as shown in figure 7. a 4-bit input data bus connects to four horizontal local buses distributed over four sec- tor rows (plane 1). a 4-bit output data bus connects to four horizontal local buses dis- tributed over four sector rows (plane 2). a 5-bit input address bus connects to five vertical express buses in same column. a 5-bit output address bus connects to five ver- tical express buses in same column. ain (input address) and aout (output address) alternate positions in horizontally aligned ram blocks. for the left-most ram blocks, aout is on the left and ain is on the right. for the right-most ram blocks, ain is on the left and aout is tied off, thus it can only be configured as a single port. for single-ported ram, ain is the read/write address port and din is the (bi-directional) data port. right-most ram blocks can be used only for single-ported memories. wen and oen connect to the vertical express buses in the same column. figure 7. ram connections (one ram block) reading and writing of the 11 - 13 ns 32 x 4 dual-port freeram are independent of each other. reading the 32 x 4 dual-port ram is completely asynchronous. latches are transparent; when load is logic 1, data flows through; when load is logic 0, data is latched. these latches are used to synchronize write adress, write enable not, and din signals for a synchronous ram. each bit in the 32 x 4 dual-port ram is also a transpar- ent latch. the front-end latch and the memory latch together form an edge-triggered flip flop. when a nibble (bit = 7) is (write) addressed and load is logic 1 and we is logic 0, 32 x 4 ram clk din ain wen oen dout aout clk clk clk clk
12 at40kel 4155b ? aero ? 06/03 data flows through the bit. when a nibble is not (write) addressed or load is logic 0 or we is logic 1, data is latched in the nibble. the two clock muxes are controlled together; they both select clock (for a synchronous ram) or they both select ? 1 ? (for an asynchronous ram). clock is obtained from the clock for the sector-column imme- diately to the left and immediately above the ram block. writing any value to the ram clear byte during configuration clears the ram (see the ? at40k/40kal configuration series? application note at www.atmel.com ). figure 8. ram logic figure 9 on page 13 shows an example of a ram macro constructed using at40kel ? s freeram cells. the macro shown is a 128 x 8 dual-ported asynchronous ram. note the very small amount of external logic required to complete the address decoding for the macro. most of the logic cells (core cells) in the sectors occupied by the ram will be unused: they can be used for other logic in the design. this logic can be automati- cally generated using the macro generators. write address din dout read address ?1? ?1? write enable not ram-clear byte dout 01 0 1 ? 1 ? clock load 5 ain aout wen din load latch load latch load latch clear 32 x 4 dual-port ram oe 4 4 5
13 at40kel 4155b ? aero ? 06/03 figure 9. ram example: 128 x 8 dual-ported ram (asynchronous) 2-to-4 decoder dout(4) dout(5) dout(6) dout(7) din dout wen oen ain aout din dout din dout wen oen din dout aout ain wen oen ain aout wen oen aout ain din dout aout ain wen oen din dout wen oen ain aout din dout aout ain wen oen din dout wen oen ain aout 2-to-4 decoder local buses express buses dedicated connections read address din(0) din(1) din(2) din(3) din(4) din(5) din(6) din(7) write address we dout(0) dout(1) dout(2) dout(3)
14 at40kel 4155b ? aero ? 06/03 clocking scheme there are eight global clock buses (gck1 - gck8) on the at40kel fpga. each of the eight dedicated global clock buses is connected to one of the dual-use global clock pins. any clocks used in the design should use global clocks where possible: this can be done by using assign pin locks to lock the clocks to the global clock locations. in addition to the eight global clocks, there are four fast clocks (fck1 - fck4), two per edge column of the array for pci specification. even the derived clocks can be routed through the global network. access points are provided in the corners of the array to route the derived clocks into the global clock network. the ids software tools handle derived clocks to global clock connections automatically if used. each column of an array has a ? column clock mux ? and a ? sector clock mux ? . the col- umn clock mux is at the top of every column of an array and the sector clock mux is at every four cells. the column clock mux is selected from one of the eight global clock buses. the clock provided to each sector column of four cells is inverted, non-inverted or tied off to ? 0 ? , using the sector clock mux to minimize the power consumption in a sector that has no clocks. the clock can either come from the column clock or from the plane 4 express bus (see figure 10 on page 15). the extreme-left column clock mux has two additional inputs, fck1 and fck2, to provide fast clocking to left-side i/os. the extreme-right column clock mux has two additional inputs as well, fck3 and fck4, to provide fast clocking to right-side i/os. the register in each cell is triggered on a rising clock edge by default. before configura- tion on power-up, constant ? 0 ? is provided to each register ? s clock pins. after configura- tion on power-up, the registers either set or reset, depending on the user ? s choice. the clocking scheme is designed to allow efficient use of multiple clocks with low clock skew, both within a column and across the core cell array.
15 at40kel 4155b ? aero ? 06/03 figure 10. clocking (for one column of cells) global clock line (buried) sector clock mux column clock mux sector clock mux express bus (plane 4; half length at edge) gck1 - gck8 repeater fck (2 per edge column of the array) ? 1 ? ? 1 ? ? 1 ? ? 1 ? } ? ? ?
16 at40kel 4155b ? aero ? 06/03 set/reset scheme the at40kel family reset scheme is essentially the same as the clock scheme except that there is only one global reset. a dedicated global set/reset bus can be driven by any user i/o, except those used for clocking (global clocks or fast clocks). the auto- matic placement tool will choose the reset net with the most connections to use the glo- bal resources. you can change this by using an rsbuf component in your design to indicate the global reset. additional resets will use the express bus network. the global set/reset is distributed to each column of the array. like sector clock mux, there is sector set/reset mux at every four cells. each sector column of four cells is set/reset by a plane 5 express bus or global set/reset using the sector set/reset mux (figure 11 on page 17). the set/reset provided to each sector column of four cells is either inverted or non-inverted using the sector reset mux. the function of the set/reset input of a register is determined by a configuration bit in each cell. the set/reset input of a register is active low (logic 0) by default. setting or resetting of a register is asynchronous. before configuration on power-up, a logic 1 (a high) is provided by each register (i.e., all registers are set at power-up).
17 at40kel 4155b ? aero ? 06/03 figure 11. set/reset (for one column of cells) each cell has a programmable set or reset global set/reset line (buried) repeater express bus (plane 5; half length at edge) sector set/reset mux any user i/o can drive global set/reset line ? 1 ? ? 1 ? ? 1 ? ? 1 ?
18 at40kel 4155b ? aero ? 06/03 i/o structure at40k has registered i/os and group enable every sector for tri-states on obuf ? s. pad the i/o pad is the one that connects the i/o to the outside world. note that not all i/os have pads: the ones without pads are called unbonded i/os. the number of unbonded i/os varies with the device size and package. these unbonded i/os are used to perform a variety of bus turns at the edge of the array. pull-up/pull-down each pad has a programmable pull-up and pull-down attached to it. this supplies a weak ? 1 ? or ? 0 ? level to the pad pin. when all other drivers are off, this control will dictate the signal level of the pad pin. the input stage of each i/o cell has a number of parameters that can be programmed either as properties in schematic entry or in the i/o pad attributes editor in ids. cmos the threshold level is a cmos-compatible level. schmitt a schmitt trigger circuit can be enabled on the inputs. the schmitt trigger is a regenera- tive comparator circuit that adds 1v hysteresis to the input. this effectively improves the rise and fall times (leading and trailing edges) of the incoming signal and can be useful for filtering out noise. delays the input buffer can be programmed to include four different intrinsic delays as specified in the ac timing characteristics. this feature is useful for meeting data hold require- ments for the input signal. drive the output drive capabilities of each i/o are programmable. they can be set to fast, medium or slow (using ids tool). the fast setting has the highest drive capability (16 ma at 5v) buffer and the fastest slew rate. medium produces a medium drive (12 ma at 5v) buffer, while slow yields a standard (4 ma at 5v) buffer. tri-state the output of each i/o can be made tri-state (0, 1 or z), open source (1 or z) or open drain (0 or z) by programming an i/o ? s source selection mux. of course, the output can be normal (0 or 1), as well. source selection mux the source selection mux selects the source for the output signal of an i/o. see figure 12 on page 21. primary, secondary and corner i/os the at40kel has three kinds of i/os: primary i/o, secondary i/o and a corner i/o. every edge cell except corner cells on the at40kel has access to one primary i/o and two secondary i/os. primary i/o every logic cell at the edge of the fpga array has a direct orthogonal connection to and from a primary i/o cell. the primary i/o interfaces directly to its adjacent core cell. it also connects into the repeaters on the row immediately above and below the adjacent core cell. in addition, each primary i/o also connects into the busing network of the three nearest edge cells. this is an extremely powerful feature, as it provides logic cells toward the center of the array with fast access to i/os via local and express buses. it can be seen from the diagram that a given primary i/o can be accessed from any logic cell on three separate rows or columns of the fpga. see figures 12a and 13a. secondary i/o every logic cell at the edge of the fpga array has two direct diagonal connections to a secondary i/o cell. the secondary i/o is located between core cell locations. this i/o
19 at40kel 4155b ? aero ? 06/03 connects on the diagonal inputs to the cell above and the cell below. it also connects to the repeater of the cell above and below. in addition, each secondary i/o also connects into the busing network of the two nearest edge cells. this is an extremely powerful fea- ture, as it provides logic cells toward the center of the array with fast access to i/os via local and express buses. it can be seen from the diagram that a given secondary i/o can be accessed from any logic cell on two rows or columns of the fpga. see figure 12a and figure 13b. corner i/o logic cells at the corner of the fpga array have direct-connect access to five separate i/os: 2 primary, 2 secondary and 1 corner i/o. corner i/os are like an extra secondary i/o at each corner of the array. with the inclusion of corner i/os, an at40kel fpga with n x n core cells always has 8n i/os. as the diagram shows, corner i/os can be accessed both from the corner logic cell and the horizontal and vertical busing networks running along the edges of the array. this means that many different edge logic cells can access the corner i/os. see figure 14.
20 at40kel 4155b ? aero ? 06/03 figure 12. south i/o (mirrored for north i/o) vcc ttl/cmos gnd pull -up pad drive tri-state pull -down delay schmitt ? 0 ? ? 1 ? ? 0 ? ? 1 ? cell cell cell pad gnd pull -up pull -down ttl/cmos drive vcc tri-state delay schmitt ? 0 ? ? 1 ? ? 1 ? ? 0 ? cell cell (a) primary i/o source select mux source select mux (b) secondary i/o (a) primary i/o
21 at40kel 4155b ? aero ? 06/03 figure 13. west i/o (mirrored for east i/o) a. primary i/0 cell "0" "1" drive tri-state "0" "1" ttl/cmo s schmitt delay pull-down pull-up gnd vcc pad cell iclk rst rst oclk b. secondary i/o
22 at40kel 4155b ? aero ? 06/03 figure 14. northwest corner i/o (similar ne/se/sw corners) "0" "1" drive tri-state "0" "1" ttl/cmos schmitt delay pull-down pull-up gnd vcc pad "0" "1" drive tri-state "0" "1" ttl/cmo s schmitt delay pull-down pull-up gnd vcc pad "0" "1" drive tri-state "0" "1" ttl/cmos schmitt delay pull-down pull-up gnd vcc pad cell cell cell cell iclk rst iclk rst iclk rst rst rst oclk oclk rst rst oclk
23 at40kel 4155b ? aero ? 06/03 electrical characteristics absolute maximum ratings* operating temperature.................................. -55 c to +125 c *note: stresses beyond those listed under absolute maximum ratings may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those listed under oper- ating conditions is not implied. exposure to abso- lute maximum rating conditions for extended periods of time may affect device reliability. storage temperature ..................................... -65 c to +150 c junction temperature .................................................. +150 c voltage on any pin with respect to ground (1) ..........................-0.5v to v cc +0.5v 1. for dc input voltage (v i ) minimum voltage of -0.5v dc, which may undershoot to -2.0v for pulses of less than 20 ns. supply voltage (v cc ) ................................................ 5v 10% esd (r zap = 1.5k, c zap = 100 pf)................................. 4000v dc and ac operating range at40kel operating temperature -55 c to +125 c v cc power supply 3.3v 0.3v input voltage level (cmos) high (v ihc ) 70% - 100% v cc low (v ilc ) 0 - 30% v cc
24 at40kel 4155b ? aero ? 06/03 note: 1. parameter based on characterization and simulation; it is not tested in production. power-on power supply requirements atmel fpgas require a minimum rated power supply current capacity to ensure proper initialization, and the power supply ramp-up time does not affect the current required. a fast ramp-up time requires more current than a slow ramp-up time. table 3. power-on supply requirements note: 1. devices are guaranteed to initialize properly at 50% of the minimum current listed above. a larger capacity power supply may result in a larger initiallization current. 2. ramp-up time is measured from 0v dc to 3.6v dc. peak current required lasts less than 2 ms, and occurs near the internal power on reset threshold voltage. dc characteristics symbol parameter conditions min typ max units v ih high-level input voltage cmos 70% v cc v ttl 2.0 v v il low-level input voltage cmos -0.3 30% v cc v ttl -0.3 0.8 v v oh high-level output voltage i oh = 4 ma v cc = v cc min 2.4 v i oh = 12 ma v cc = 3.0v 2.4 v i oh = 16 ma v cc = 3.0v 2.4 v v ol low-level output voltage i ol = -4 ma v cc = 3.0v 0.4 v i ol = -12 ma v cc = 3.0v 0.4 v i ol = -16 ma v cc = 3.0v 0.4 v i ih high-level input current v in = v cc max -5 5 a with pull-down, v in = v cc 20 75 300.0 a i il low-level input current v in = v ss -5 5 a with pull-up, v in = v ss -300.0 -50 -20 a i ozh high-level tri-state output leakage current without pull-down, v in = v cc max -5 5 a with pull-down, v in = v cc max 20 300.0 a i ozl low-level tri-state output leakage current without pull-up, v in = v ss -5 ma with pull-up, v in = v ss for con -500 -150.0 -110 a i cc standby current consumption standby, unprogrammed 1 5 ma c in input capacitance all pins 10.0 pf description maximum current (1)(2) maximum current supply 1.2 a
25 at40kel 4155b ? aero ? 06/03 ac timing characteristics delays are based on fixed loads and are described in the notes. maximum times based on worst case: v cc = 3.0v, temperature = 125 c. minimum times based on best case: v cc = 3.60v, temperature = -55 c. maximum delays are the average of t pdlh and t pdhl . ac timing characteristics all input i/o characteristics measured from v ih of 50% of v dd at the pad (cmos threshold) to the internal v ih of 50% of v dd . all output i/o characteristics are measured as the average of t pdlh and t pdhl to the pad v ih of 50% of v dd . cell function parameter path at40kel units notes core 2-input gate t pd (max) x/y -> x/y 2.9 ns 1 unit load 3-input gate t pd (max) x/y/z -> x/y 3.1 ns 1 unit load 3-input gate t pd (max) x/y/w -> x/y 3.5 ns 1 unit load 4-input gate t pd (max) x/y/w/z -> x/y 3.5 ns 1 unit load fast carry t pd (max) y -> y 2.8 ns 1 unit load fast carry t pd (max) x -> y 2.6 ns 1 unit load fast crry t pd (max) y -> x 2.8 ns 1 unit load fast carry t pd (max) x -> x 2.9 ns 1 unit load fast carry t pd (max) w -> y 3.5 ns 1 unit load fast carry t pd (max) w -> x 3.5 ns 1 unit load fast carry t pd (max) z -> y 3.1 ns 1 unit load fast carry t pd (max) z -> x 3.0 ns 1 unit load dff t pd (max) clk -> x/y 4.3 ns 1 unit load dff t pd (max) r -> x/y 4.1 ns 1 unit load dff t pd (max) s -> x/y 2.8 ns 1 unit load dff t pd (max) q -> w 4.3 ns incremental -> l t pd (max) x/y -> l 2.5 ns 1 unit load local output enable t pzx (max) oe -> l 2.9 ns 1 unit load local output enable t pxz (max) oe -> l 0.9 ns cell function parameter path at40kel units notes repeaters repeater t pd (max) l -> e 1.3 ns 1 unit load repeater t pd (max) e -> e 1.3 ns 1 unit load repeater t pd (max) l -> l 1.3 ns 1 unit load repeater t pd (max) e -> l 1.3 ns 1 unit load repeater t pd (max) e -> io 0.7 ns 1 unit load repeater t pd (max) l -> io 0.7 ns 1 unit load
26 at40kel 4155b ? aero ? 06/03 cell function parameter path at40kel units notes i/o input t pd (max) pad -> x/y 5.4 ns no extra delay input t pd (max) pad -> x/y 7.6 ns 1 extra delay input t pd (max) pad -> x/y 11.4 ns 2 extra delays input t pd (max) pad -> x/y 14.9 ns 3 extra delays output, slow t pd (max) x/y/e/l -> pad 16.0 ns 50 pf load output, medium t pd (max) x/y/e/l -> pad 14.8 ns 50 pf load output, fast t pd (max) x/y/e/l -> pad 11.2 ns 50 pf load output, slow t pzx (max) oe -> pad 16.4 ns 50 pf load output, slow t pxz (max) oe -> pad 5.1 ns 50 pf load output, medium t pzx (max) oe -> pad 14.1 ns 50 pf load output, medium t pxz (max) oe -> pad 9.1 ns 50 pf load output, fast t pzx (max) oe -> pad 11.4 ns 50 pf load output, fast t pxz (max) oe -> pad 9.5 ns 50 pf load
27 at40kel 4155b ? aero ? 06/03 ac timing characteristics clocks and reset input buffers are measured from a v ih of 1.5v at the input pad to the internal v ih of 50% of v cc . maximum times for clock input buffers and internal drivers are measured for rising edge delays only. notes: 1. cmos buffer delays are measured from a v ih of 1/2 v cc at the pad to the internal v ih at a. the input buffer load is constant. 2. buffer delay is to a pad voltage of 1.5v with one output switching. 3. parameter based on characterization and simulation; not tested in production. 4. exact power calculation is available in atmel fpga designer software. cell function parameter path device units notes global clocks and set/reset gck input buffer t pd (max) pad -> clock at40kel 3.3 ns rising edge clock fck input buffer t pd (max) pad -> clock at40kel 1.9 ns rising edge clock clock column driver t pd (max) clock -> colclk at40kel 1.7 ns rising edge clock clock sector driver t pd (max) colclk -> secclk at40kel 0.8 ns rising edge clock gsrn input buffer t pd (max) colclk -> secclk at40kel 10.3 ns global clock to output t pd (max) clock pad -> out at40kel 21.3 ns rising edge clock fully loaded clock tree rising edge dff 20 ma output buffer 50 pf pin load fast clock to output t pd (max) clock pad -> out at40kel 19.9 ns rising edge clock fully loaded clock tree rising edge dff 20 ma output buffer 50 pf pin load
28 at40kel 4155b ? aero ? 06/03 ac timing characteristics cell function parameter path at40kel units notes async ram write t wecyc (min) cycle time 28 ns write t wel (min) we 6.5 ns pulse width low write t weh (min) we 6.5 ns pulse width high write t setup (min) wr addr setup -> we 7.0 ns write t hold (min) wr addr hold -> we 0.0 ns write t setup (min) din setup -> we 6.5 ns write t hold (min) din hold -> we 0.0 ns write t hold (min) oe hold -> we 0.0 ns write/read t pd (max) din -> dout 14.1 ns rd addr = wr addr read t pd (max) rd addr -> dout 13.1 ns read t pzx (max) oe -> dout 4.5 ns read t pxz (max) oe -> dout 4.5 ns sync ram write t cyc (min) cycle time 28 ns write t clkl (min) clk 6.5 ns pulse width low write t clkh (min) clk 6.5 ns pulse width high write t setup (min) we setup -> clk 5.0 ns write t hold (min) we hold -> clk 0.0 ns write t setup (min) wr addr setup -> clk 6.5 ns write t hold (min) wr addr hold -> clk 0.0 ns write t setup (min) wr data setup -> clk 5.1 ns write t hold (min) wr data hold -> clk 0.0 ns write/read t pd (max) din -> dout 14.1 ns rd addr = wr addr write/read t pd (max) clk -> dout 7.9 ns rd addr = wr addr read t pd (max) rd addr -> dout 13.1 ns read t pzx (max) oe -> dout 4.5 ns read t pxz (max) oe -> dout 4.5 ns
29 at40kel 4155b ? aero ? 06/03 freeram asynchronous timing characteristics single port write/read dual port write with read dual port read we addr data t clkh t wcs t acs t dch t wch t ach 012 clk t oxz t dcs 3 oe t ozx t ad we wr addr wr data rd data t clkh t wcs t acs t cyc t wch t cd t ach = wr addr 1 rd addr 01 2 clk t clkl t dcs t dch rd addr data 01 t ozx oe t oxz t ad
30 at40kel 4155b ? aero ? 06/03 freeram synchronous timing characteristics single port write/read dual port write with read we addr data t clkh t wcs t acs t dch t wch t ach 012 clk t oxz t dcs 3 oe t ozx t ad we wr addr wr data rd data t clkh t wcs t acs t cyc t wch t cd t ach = wr addr 1 rd addr 01 2 clk t clkl t dcs t dch
at40kal/el 31 4155a ? aero ? 06/02 dual port read rd addr data 01 t ozx oe t oxz t ad
at40kal/el 32 4155a ? aero ? 06/02 table 4. pad/pin assignment 384 i/o mqfpf160 gnd 1 i/o1, gck1 (a16) 2 i/o2 (a17) 3 i/o3 4 i/o4 5 i/o5 (a18) 6 i/o6 (a19) 7 gnd i/o7 i/o8 i/o9 i/o10 i/o11 i/o12 vcc gnd i/o13 i/o14 i/o15 8 i/o16 9 i/o17 i/o18 gnd i/o19 i/o20 i/o21 i/o22 i/o23 i/o24 gnd 10 i/o25, fck1 11 i/o26 12 i/o27 (a20) 13 i/o28 (a21) 14 vcc i/o29 i/o30 gnd i/o31 i/o32 i/o33 i/o34 i/o35 i/o36 gnd vcc i/o37 i/o38 i/o39 i/o40 i/o41 i/o42 gnd i/o43 15 i/o44 16 i/o45 i/o46 i/o47 (a22) 17 i/o48 (a23) 18 gnd 19 vcc 20 i/o49 21 i/o50 22 i/o51 i/o52 i/o53 23 i/o54 24 gnd i/o55 i/o56 i/o57 i/o58 i/o59 i/o60 vcc gnd i/o61 i/o62 i/o63 i/o64 i/o65 384 i/o mqfpf160 i/o66 gnd i/o67 i/o68 vcc i/o69 25 i/o70 26 i/o71 27 i/o72, fck2 28 gnd 29 i/o73 i/o74 i/o75 i/o76 i/o77 i/o78 gnd i/o79 i/o80 i/o81 i/o82 i/o83 30 i/o84 31 gnd vcc i/o85 i/o86 i/o87 i/o88 i/o89 32 i/o90 33 gnd i/o91 i/o92 i/o93 34 i/o94 35 i/o95 (ots ) (1) 36 i/o96, gck2 37 m1 38 gnd 39 m0 40 vcc 41 m2 42 384 i/o mqfpf160
at40kal/el 33 4155a ? aero ? 06/02 i/o97, gck3 43 i/o98 (hdc) 44 i/o99 45 i/o100 46 i/o101 47 i/o102 (ldc) 48 gnd i/o103 i/o104 i/o105 i/o106 i/o107 i/o108 vcc gnd i/o109 49 i/o110 50 i/o111 i/o112 i/o113 i/o114 gnd i/o115 i/o116 i/o117 i/o118 i/o119 i/o120 gnd 51 i/o121 52 i/o122 53 i/o123 54 i/o124 55 vcc i/o125 i/o126 gnd i/o127 i/o128 i/o129 i/o130 i/o131 i/o132 384 i/o mqfpf160 gnd vcc i/o133 i/o134 i/o135 i/o136 i/o137 56 i/o138 57 gnd i/o139 i/o140 i/o141 i/o142 i/o143 (d15) 58 i/o144 (init) 59 vcc 60 gnd 61 i/o145 (d14) 62 i/o146 (d13) 63 i/o147 i/o148 i/o149 i/o150 gnd i/o151 64 i/o152 65 i/o153 i/o154 i/o155 i/o156 vcc gnd i/o157 i/o158 i/o159 i/o160 i/o161 i/o162 gnd i/o163 i/o164 vcc 384 i/o mqfpf160 i/o165 (d12) 66 i/o166 (d11) 67 i/o167 68 i/o168 69 gnd 70 i/o169 i/o170 i/o171 i/o172 i/o173 i/o174 gnd i/o175 i/o176 i/o177 i/o178 i/o179 71 i/o180 72 gnd vcc i/o181 i/o182 i/o183 (d10) 73 i/o184 (d9) 74 i/o185 i/o186 gnd i/o187 i/o188 i/o189 75 i/o190 76 i/o191 (d8) 77 i/o192, gck4 78 gnd 79 con 80 vcc 81 reset 82 i/o193 (d7) 83 i/o194, gck5 84 i/o195 85 384 i/o mqfpf160
at40kal/el 34 4155a ? aero ? 06/02 i/o196 86 i/o197 i/o198 gnd i/o199 i/o200 i/o201 i/o202 i/o203 i/o204 vcc gnd i/o205 (d6) 87 i/o206 88 i/o207 89 i/o208 90 i/o209 i/o210 gnd i/o211 i/o212 i/o213 i/o214 i/o215 i/o216 gnd 91 i/o217 i/o218 i/o219, fck3 92 i/o220 93 vcc i/o221 (d5) 94 i/o222 (cs0) 95 gnd i/o223 i/o224 i/o225 i/o226 i/o227 i/o228 gnd vcc 384 i/o mqfpf160 i/o229 i/o230 i/o231 i/o232 i/o233 i/o234 gnd i/o235 96 i/o236 97 i/o237 i/o238 i/o239(d4) 98 i/o240 99 vcc 100 gnd 101 i/o241 (d3) 102 i/o242 (check ) 103 i/o243 i/o244 i/o245 104 i/o246 105 gnd i/o247 i/o248 i/o249 i/o250 i/o251 i/o252 vcc gnd i/o253 i/o254 i/o255 i/o256 i/o257 i/o258 gnd i/o259 (d2) 106 i/o260 107 vcc i/o261 108 i/o262,fck4 109 i/o263 384 i/o mqfpf160 i/o264 gnd 110 i/o265 i/o266 i/o267 i/o268 i/o269 i/o270 gnd i/o271 i/o272 i/o273 111 i/o274 112 i/o275 i/o276 gnd vcc i/o277 (d1) 113 i/o278 114 i/o279 i/o280 i/o281 i/o282 gnd i/o283 i/o284 i/o285 115 i/o286 116 i/o287 (d0) 117 i/o288, gck6 (csout ) 118 cclk 119 vcc 120 tstclk 121 gnd 122 i/o289 (a0) 123 i/o290, gck7 (a1) 124 i/o291 125 i/o292 126 i/o293 i/o294 gnd 384 i/o mqfpf160
at40kal/el 35 4155a ? aero ? 06/02 note: 1.shared with tstclk i/o295 i/o296 i/o297 (cs1 ,a2) 127 i/o298 (a3) 128 i/o299 i/o300 vcc gnd i/o301 (1) 121 (1) nc i/o302 i/o303 129 i/o304 130 i/o305 i/o306 gnd i/o307 i/o308 i/o309 i/o310 i/o311 i/o312 gnd 131 i/o313 132 i/o314 133 i/o315 i/o316 vcc i/o317 i/o318 gnd i/o319 i/o320 i/o321 i/o322 i/o323 i/o324 gnd vcc i/o325 (a4) 134 i/o326 (a5) 135 i/o327 i/o328 136 384 i/o mqfpf160 i/o329 137 i/o330 138 gnd i/o331 i/o332 i/o333 i/o334 i/o335 (a6) 139 i/o336 (a7) 140 gnd 141 vcc 142 i/o337 (a8) 143 i/o338 (a9) 144 i/o339 i/o340 i/o341 i/o342 gnd i/o343 145 i/o344 146 i/o345 i/o346 i/o347 (a10) 147 i/o348 (a11) 148 vcc gnd i/o349 i/o350 i/o351 i/o352 i/o353 i/o354 gnd i/o355 i/o356 vcc i/o357 i/o358 i/o359 149 i/o360 150 gnd 151 384 i/o mqfpf160 i/o361 i/o362 i/o363 i/o364 i/o365 i/o366 gnd i/o367 i/o368 i/o369 152 i/o370 153 i/o371 (a12) 154 i/o372 (a13) 155 gnd vcc i/o373 i/o374 i/o375 i/o376 i/o377 i/o378 gnd i/o379 i/o380 i/o381 156 i/o382 157 i/o383 (a14) 158 i/o384, gck8 (a15) 159 vcc 160 384 i/o mqfpf160
36 at40kel 4155b ? aero ? 06/03 part/package availability and user i/o counts (including dual-function pins) note: 1. contact atmel for availability. package at40kel040 mqfpf 160 130 mqfpf 256 (1) 193 mqfpf 352 (1) 289
37 at40kel 4155b ? aero ? 06/03 ordering information part number temperature range quality flow AT40KEL040KW1M-E 25 c engineering samples at40kel040kw1m -55 to +125 c standard mil at40kel040kw1mmq -55 to +125 cqml q at40kel040kw1smb -55 to +125 cqml v at40kel040kw1ssb -55 to +125 c scc b
38 at40kel 4155b ? aero ? 06/03 package drawing multilayer quad flat pack (mqfp) 160-pin
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